AMD Patents High-Bandwidth RAM Architecture to Double DDR5 Speeds
AMD has unveiled a groundbreaking patent for a new RAM architecture aimed at overcoming the bandwidth bottlenecks of DDR5 memory. The innovation, dubbed High-Bandwidth Dual Inline Memory Module (HB-DIMM), promises to double data rates to 12.8 Gbps on the memory bus, far exceeding DDR5's native 6.4 Gbps. This development comes as DDR5 struggles to keep pace with the escalating demands of high-performance gaming, graphics processors, and servers.
Key Features of the HB-DIMM Architecture
The patent introduces several advanced elements to enhance memory performance:
- Dual-Speed Data Buffering: Multiple DRAM chips connect to data buffer chips that transmit data at twice the speed of standard memory chips, enabling non-interleaved transfers for simpler signal integrity and lower latency.
- Pseudo Channels and Intelligent Routing: A register clock driver (RCD) uses a chip identifier (CID) bit to route commands to independently addressable pseudo-channels, boosting parallel access and throughput.
- Flexible Operating Modes: Supports 1n and 2n modes for optimized clocking, along with programmable switches between pseudo-channel and quad-rank setups, ensuring compatibility with DDR5 standards.
According to the patent, "The memory bandwidth required for applications such as high-performance graphics processors... are outpacing the roadmap of bandwidth improvements for DDR DRAM chips." This architecture leverages existing DDR5 chips without major manufacturing overhauls, making it a scalable upgrade for future systems.
Implications for Gaming and AI
If implemented, HB-DIMM could revolutionize RAM performance in high-end PCs, AI workloads, and data centers by addressing DDR5's stagnation. AMD's move aligns with its recent patents, including blower fan designs for laptops and smart cache systems for processors, signaling a push toward next-gen hardware innovation. The biggest beneficiaries of this kind of advancement would be iGPUs, which rely on RAM as VRAM. The IP described here could be integrated into the next generation of handhelds and consoles, bringing the performance of costly high-end chips like the Strix Halos to the masses.
This patent, accessible via WIPO, raises questions about the future of RAM evolution amid rising computational needs.
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